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74ACTQ32 Quiet Series Quad 2-Input OR Gate
March 1993 Revised September 2000
74ACTQ32 Quiet Series Quad 2-Input OR Gate
General Description
The ACTQ320 contains four, 2-input OR gates and utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.
Features
s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Minimum 4 kV ESD protection s TTL-compatible inputs s Outputs source/sink 24 mA
Ordering Code:
Order Number 74ACT32SC 74ACT32SJ 74ACT32PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names An, Bn On Descriptions Inputs Outputs
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS010893
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74ACTQ32
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) PDIP
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 50 mA -65C to +150C 300 mA
140C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
Note 1: Absolute maximum ratings are values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside of databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 -0.6 1.9 1.2 2.0 1.5 -1.2 2.2 0.8 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 2.0 2.0 0.8 0.8 4.4 5.4 3.70 4.70 0.1 0.1 0.50 0.50 1.0 1.6 50 -50 40.0 TA = -55C to +125C TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 20.0 A mA mA mA A V V V V V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = - 24 mA IOH = - 24 mA (Note 2) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Figures 1, 2 (Note 4)(Note 5) Figures 1, 2 (Note 4)(Note 5) (Note 4)(Note 6) (Note 4)(Note 6)
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: DIP Package. Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHZ.
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74ACTQ32
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 7) tPLH tPHL tOSHL tOSLH Propagation Delay Data to Output Propagation Delay Data to Output Output to Output Skew (Note 8) 5.0 5.0 5.0 Min 2.5 2.0 TA = +25C CL = 50 pF Typ 6.0 6.0 0.5 Max 6.5 6.5 1.0 TA = -40C to +85C CL = 50 pF Min 2.5 2.5 Max 7.0 7.0 1.0 ns ns ns Units
Note 7: Voltage Range 5.0 is 5.0V 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 68 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74ACTQ32
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as V ILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACTQ devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ32
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
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74ACTQ32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74ACTQ32 Quiet Series Quad 2-Input OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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